Integrated circuit and method
US7361599B2 · kind B2 · utility
2Cited by
1References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2005 |
| Grant date | Apr 22, 2008 |
| Priority date | — |
| Expiry date | Aug 18, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/682
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.