Method for multi-layer resist plasma etch
US7361607B2 · kind B2 · utility
6Cited by
4References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 22, 2006 |
| Grant date | Apr 22, 2008 |
| Priority date | — |
| Expiry date | Nov 22, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32139
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for etching a multi-layer resist defined over a substrate in a plasma etch chamber is provided. The method initiates with introducing the substrate having a pattern defined on a first layer of the multi-layer resist into the etch chamber. SO2 gas flows into the etch chamber and a plasma is struck in the etch chamber while flowing the SO2 gas. The multi-layer resist is then etched.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.