Mask patterns for semiconductor device fabrication and related methods
US7361609B2 · kind B2 · utility
22Cited by
5References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2005 |
| Grant date | Apr 22, 2008 |
| Priority date | — |
| Expiry date | Jan 17, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31144
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming an integrated circuit device may include forming a resist pattern on a layer of an integrated circuit device with portions of the layer being exposed through openings of the resist pattern. An organic-inorganic hybrid siloxane network film may be formed on the resist pattern. Portions of the layer exposed through the resist pattern and the organic-inorganic hybrid siloxane network film may then be removed. Related structures are also discussed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.