Semiconductor assembly and packaging for high current and low inductance
US7361977B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 15, 2005 |
| Grant date | Apr 22, 2008 |
| Priority date | — |
| Expiry date | Sep 7, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device comprising a semiconductor chip (110) having a side edge (111) and a plurality of metal bond pads (120, 121) near the edge; the pads are aligned to form rows (130, 131) parallel to the edge. The device further includes a leadframe (100) having leads (140 . . . ) oriented with one end (140a . . . ) towards the chip edge and spaced from it by a gap (150); the chip is attached to the leadframe. Ends of selected leads are connected by a metal cross bar (160) parallel to the chip edge. Substantially parallel bond wires (170) are crossing the gap to connect each chip pad either to the crossbar or to a non-selected lead end. In a preferred lead arrangement, the selected leads alternate with non-selected leads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.