Memory arrangement having a plurality of RAM chips

US7362650B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Helmut Kandolf · Hersbruck, DE
• Sven Kalms · Munich, DE
• Maksim Kuzmenka · Birkenfeld, DE
• Michael Hausmann · Graz, AT

Key dates

• Filing date: Mar 30, 2006
• Grant date: Apr 22, 2008
• Expiry date: Mar 30, 2026

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C11/4096
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Embodiments of the invention provide a memory arrangement having an even number k=4 of physically spaced RAM chips, on each of which it is possible for m data items to be simultaneously written or read via an m-bit data bus, also having a register for buffer-storing and transmitting n respective parallel data bits as a packet between an n-bit parallel port and the data buses, and having a selection device which responds to selection bits in order to select a respective separate cell group within the plurality of the chips for each of the disjoint m-bit groups (d) of the n-bit packet. The k chips are classified into q=2 disjoint chip groups, each of which comprises k/q chips which differ as little as possible from one another in terms of their distance from the register. The number m is chosen to be equal to q*n/k, and the selection device is designed to select a respective separate chip from the same chip group and a cell group in this chip for each m-bit group of the same n-bit packet.