Content addressable memories (CAMs) based on a binary CAM and having at least three states
US7363424B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2007 |
| Grant date | Apr 22, 2008 |
| Priority date | — |
| Expiry date | Jan 4, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Content addressable memories are disclosed that provide at least three states and are based on existing binary CAM devices. A higher order CAM having at least three states comprises a binary CAM having two binary bits; and a logic circuit to configure the two binary bits as a single CAM bit having said at least three states. The three states include a don't care state, a logic 0 state and a logic 1 state. The logic circuit may be embodied as two OR gates. The first match search (MS) input and a first wild card (WC) input of the higher order CAM are applied to inputs of the two OR gates and the outputs of the two OR gates are applied to the wild card (WC) inputs of the binary CAM. The match search (MS) inputs of the binary CAM are tied to a power supply voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.