Performing virtual to global address translation in processing subsystem
US7363462B2 · kind B2 · utility
6Cited by
8References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2004 |
| Grant date | Apr 22, 2008 |
| Priority date | — |
| Expiry date | Jul 1, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0815
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system may include a plurality of nodes. Each node may include one or more active devices coupled to one or more memory subsystems. Each active device in one of the plurality of nodes includes a memory management unit configured to receive a virtual address generated within that active device and to responsively output a global address and associated information that identifies a translation function. The memory subsystem in the one of the plurality of nodes is configured to apply the translation function identified in the information to the global address to generate a local physical address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.