Method for manufacturing semiconductor devices
US7364956B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2005 |
| Grant date | Apr 29, 2008 |
| Priority date | — |
| Expiry date | Oct 4, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing semiconductor devices includes a step of etching a sample including an interlayer insulating layer containing Al2O3 and a polysilicon or SiO2 layer in contact with the interlayer insulating layer using a plasma etching system. The interlayer insulating layer is etched with a gas mixture containing BCl3, Ar, and CH4 or He. The gas mixture further contains Cl2. The interlayer insulating layer is etched in such a manner that a time-modulated high-frequency bias voltage is applied to the sample. The interlayer insulating layer is etched in such a manner that the sample is maintained at a temperature of 100° C. to 200° C. The interlayer insulating layer and the polysilicon or SiO2 layer are separately etched in different chambers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.