Damascene replacement metal gate process with controlled gate profile and length using Si1-xGex as sacrificial material
US7365015B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2004 |
| Grant date | Apr 29, 2008 |
| Priority date | — |
| Expiry date | Jul 13, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28079
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a metal gate in a wafer. PolySi1-xGex and polysilicon are used to form a tapered groove. Gate oxide, PolySi1-xGex, and polysilicon is deposited on a wafer. A resist pattern is formed. A portion of the polysilicon, PolySi1-xGex, and gate oxide is removed to provide a tapered profile. The resist is removed; a dielectric liner is deposited, and then at least a portion of the dielectric liner is removed, thereby exposing the polysilicon and leaving the dielectric liner in contact with the polysilicon, PolyS1-xGex, and gate oxide. A dielectric is deposited, and a portion is removed thereby exposing the polysilicon. The polysilicon, PolySi1-xGex, and gate oxide is removed from inside the dielectric liner, thereby leaving a tapered gate groove. Metal is then deposited in the groove.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.