MOSFET structure with ultra-low K spacer

US7365378B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Elbert E. Huang · Carmel, US
• Philip J. Oldiges · Lagrangeville, US
• Ghavam G. Shahidi · Pound Ridge, US
• Christy S. Tyberg · Mahopac, US
• Xinlin Wang · Irvine, US
• Robert L. Wisnieff · Ridgefield, US

Key dates

• Filing date: Mar 31, 2005
• Grant date: Apr 29, 2008
• Expiry date: Mar 25, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0212

Abstract

A MOSFET structure and method of fabricating the structure incorporates a multi-layer sidewall spacer to suppress parasitic overlap capacitance between the gate conductor and the source/drain extensions without degrading drive current and, thereby, effecting overall MOSFET performance. The multi-layer sidewall spacer is formed with a gap layer having a dielectric constant equal to one and a permeable low-K (e.g., less than 3.5) dielectric layer. Alternatively, the multi-layer sidewall spacer is formed with a first L-shaped dielectric layer having a permittivity value of less than approximately three and a second dielectric layer. The multi-layer spacer may also have a third nitride or oxide spacer layer. This third spacer layer provides increased structural integrity.