Compact SRAMs and other multiple transistor structures
US7365398B2 · kind B2 · utility
15Cited by
7References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2005 |
| Grant date | Apr 29, 2008 |
| Priority date | — |
| Expiry date | Feb 11, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/00
Abstract
A highly dense form of static random-access memory (SRAM) takes advantage of transistor gates on both sides of silicon and high interconnectivity made possible by the complex form of silicon-on-insulator and three-dimensional integration. This technology allows one to form p-channel and n-channel devices very compactly by taking advantage of placement of gates on both sides, making common contacts and dense interconnections in 3D.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.