Multi-chip structure
US7365418B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 22, 2006 |
| Grant date | Apr 29, 2008 |
| Priority date | — |
| Expiry date | Sep 22, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1627
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-chip structure at least including a first chip, a second chip and a first thermal-conductive layer is provided. The first chip has a first surface and a plurality of first pads disposed on the first surface. The second chip has a second surface facing the first surface and a plurality of second pads disposed on the second surface. The first thermal-conductive layer is disposed between the first chip and the second chip and includes a thermal-conductive area, a plurality of first electrical connection members and a plurality of first dielectric areas. The first electrical connection members disposed in the first thermal-conductive layer are used to electrically connect the first surface and the second surface. The first dielectric areas surround and insulate the first electrical connection members from the thermal-conductive area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.