Method for modifying data more than once in a multi-level cell memory location within a memory array
US7366017B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 22, 2006 |
| Grant date | Apr 29, 2008 |
| Priority date | — |
| Expiry date | Aug 22, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for programming one or more bits in an upper page twice depending on the value in a corresponding bit in a corresponding lower page in a multi-level cell device. The method includes the steps of initializing the bit in the lower page and the bit in the upper page by storing a value of one in each of the bits. One or more bits in the lower page are then programmed such that a one is stored in the one or more bits of the lower page. One or more bits in the upper page are then programmed such that a one is stored in the one or more bits of the upper page. The one or more bits in the upper page are then reprogrammed such that the value in the one or more bits of the upper page transitions from a one to a zero. The transition from a one to a zero in the one or more bits of the upper page is used to mark for performance of a block management function the block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.