Method and apparatus for high-speed input sampling
US7366942B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 12, 2004 |
| Grant date | Apr 29, 2008 |
| Priority date | — |
| Expiry date | Jan 17, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A signal sampler and method for high-speed input sampling of a signal are disclosed. A first sampler samples a data signal at a rising edge of a clock signal and generates a first sampled signal. A second sampler samples the data signal at a falling edge of an inverted clock signal and generates a second sampled signal. The first and second sampled signals may be combined to determine the next signal sampler output. An evaluation may include asserting the output signal if the first and second sampled signals are asserted, negating the output signal if the first and second sampled signal are negated, and toggling the output signal if the first and second sampled signals are in opposite logic states. The signal sampler and method of signal sampling may be incorporated in a semiconductor device, which may be fabricated on a semiconductor wafer and included in an electronic system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.