Method and system for parametric reduction of sequential designs
US7367002B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2005 |
| Grant date | Apr 29, 2008 |
| Priority date | — |
| Expiry date | Feb 4, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, system and computer program product for performing parametric reduction of sequential designs. According to an embodiment of the present invention, the method includes receiving an initial design including one or more primary inputs, one or more targets, and one or more state elements. A cut of the initial design including one or more cut gates is identified, and a relation of one or more values producible to the one or more cut gates in terms of the one or more primary inputs and the one or more state elements is computed. The relation is synthesized to form a gate set, and an abstracted design is formed from the gate set. Verification is performed on the abstracted design to generate verification results.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.