Framework for integrated intra- and inter-loop aggregation of contiguous memory accesses for SIMD vectorization
US7367026B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2004 |
| Grant date | Apr 29, 2008 |
| Priority date | — |
| Expiry date | Feb 10, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/445
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, computer program product, and information handling system for generating loop code to execute on Single-Instruction Multiple-Datapath (SIMD) architectures, where the loop contains multiple non-stride-one memory accesses that operate over a contiguous stream of memory is disclosed. A preferred embodiment identifies groups of isomorphic statements within a loop body where the isomorphic statements operate over a contiguous stream of memory over the iteration of the loop. Those identified statements are then converted into virtual-length vector operations. Next, the hardware's available vector length is used to determine a number of virtual-length vectors to aggregate into a single vector operation for each iteration of the loop. Finally, the aggregated, vectorized loop code is converted into SIMD operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.