Method for fabricating a transformer integrated with a semiconductor structure
US7367113B2 · kind B2 · utility
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13References
10Claims
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Assignee
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Key dates
| Filing date | Apr 6, 2006 |
| Grant date | May 6, 2008 |
| Priority date | — |
| Expiry date | Apr 6, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49128
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A substrate is provided and a top interconnection metal layer and a primary winding layer are formed thereon. Then a passivation layer having a plurality of via exposed parts of the top interconnection metal layer is formed on the substrate. A secondary winding layer and at least a bonding pad are formed on the passivation layer. The bonding pad electrically connects to the top interconnection metal layer through the via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.