Multi-layer interconnect structure for semiconductor devices
US7368379B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2005 |
| Grant date | May 6, 2008 |
| Priority date | — |
| Expiry date | Jan 29, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76877
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
An interconnect structure for a semiconductor device and its method of manufacture is provided. The interconnect structure includes a multi-layer structure having one or more stress-relief layers. In an embodiment, stress-relief layers are positioned between layers of electroplated copper or other conductive material. The stress-relief layer counteracts stress induced by the conductive material and helps prevent or reduce a pull-back void. For an interconnect structure using electroplated copper, the stress-relief layer may be formed by temporarily reducing the electroplating current, thereby causing a thin film of copper having a larger grain size to be formed between other layers of copper. The larger grain size typically exhibits more of a compressive stress than copper with a smaller grain size. The stress relief layer may also be formed of other materials, such as SIP-Cu, Ta, SiC, or the like.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.