Buffer
US7368953B2 · kind B2 · utility
1Cited by
4References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 6, 2006 |
| Grant date | May 6, 2008 |
| Priority date | — |
| Expiry date | Feb 5, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A buffer is disclosed. The buffer may include a buffer controller for buffering a refresh signal enabled in an auto-refresh operation synchronously with an external clock signal, a logic circuit for performing a logic operation with respect to an output signal from the buffer controller and a specific signal to output a control signal, and an internal clock generator controlled by the control signal from the logic circuit for buffering the external clock signal and generating internal clock signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.