Method and apparatus to prevent high voltage supply degradation for high-voltage latches of a non-volatile memory
US7369446B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2006 |
| Grant date | May 6, 2008 |
| Priority date | — |
| Expiry date | Jul 13, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved cross-coupled CMOS high-voltage latch that is used for storing data bits to be written to memory cells of a non-volatile memory is provided with a switching circuit that, during writing of data bits into the memory cells of the latch, provides a high series impedance between one leg of the latch and ground to limit leakage current. A large number of latches are connected in parallel and their accumulated leakage currents are limited by the switching circuit to prevent overload of a high-voltage generator, such as a charge pump circuit, for the high-voltage latch, so that data can be properly written in the memory cells of the non-volatile memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.