Mechanism for avoiding check stops in speculative accesses while operating in real mode
US7370177B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2003 |
| Grant date | May 6, 2008 |
| Priority date | — |
| Expiry date | Jan 20, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3842
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and processor for avoiding check stops in speculative accesses. An execution unit, e.g., load/store unit, may be coupled to a queue configured to store instructions. A register, coupled to the execution unit, may be configured to store a value corresponding to an address in physical memory. When the processor is operating in real mode, the execution unit may retrieve the value stored in the register. Upon the execution unit receiving a speculative instruction, e.g., speculative load instruction, from the queue, a determination may be made as to whether the address of the speculative instruction is at or below the retrieved value. If the address of the speculative instruction is at or below this value, then the execution unit may safely speculatively execute this instruction while avoiding a check stop since all the addresses at or below this value are known to exist in physical memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.