Method and apparatus for testing a memory array
US7370249B2 · kind B2 · utility
1Cited by
10References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2004 |
| Grant date | May 6, 2008 |
| Priority date | — |
| Expiry date | Feb 18, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for testing a memory array. More particularly, embodiments of the invention relate to a memory array testing architecture in which a memory array within a device under test (DUT) is able to be tested at speeds substantially similar to those under typical operating conditions of the memory array without incurring significant die real estate and power penalties.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.