Method and circuit for collecting memory failure information
US7370251B2 · kind B2 · utility
35Cited by
9References
54Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2003 |
| Grant date | May 6, 2008 |
| Priority date | — |
| Expiry date | Jan 4, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and circuit for collecting memory failure information on-chip and unloading the information in real time while performing a test of memory embedded in a circuit comprises, for each column or row of a memory under test, testing each memory location of the column or row according to a memory test algorithm under control of a first clock, selectively generating a failure summary on-circuit while testing each column or row of the memory; and transferring the failure summary from the circuit under control of a second clock within the time required to test the next column or row, if any, of the memory under test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.