Method for mapping logic design memory into physical memory devices of a programmable logic device
US7370291B2 · kind B2 · utility
7Cited by
8References
66Claims
0Family size
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Key dates
| Filing date | Feb 28, 2005 |
| Grant date | May 6, 2008 |
| Priority date | — |
| Expiry date | Nov 25, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided for mapping logic design memory into physical memory devices of a programmable logic device. User constraints and physical constraints may be taken into account in generating the mapping solution. Functional block layout on the programmable logic device may be taken into account when generating the mapping solution. Multiple types of physical memory types may be considered and logic design memory may be mapped to those types of physical memory devices that are determined to be the most appropriate. A mapping solution may be optimized using, for example, simulated annealing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.