Process for fabricating an integrated circuit package with reduced mold warping
US7371610B1 · kind B1 · utility
63Cited by
55References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2004 |
| Grant date | May 13, 2008 |
| Priority date | — |
| Expiry date | Oct 18, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for fabricating an integrated circuit package includes mounting a semiconductor die on a first surface of a metal carrier and forming electrical connections between the semiconductor die and ones of a plurality of contacts on the metal carrier. Next, using a molding material in a mold, the semiconductor die and the contacts are molded in the molding material, between the metal carrier and a metal strip. The metal carrier and the metal strip are etched away and the integrated circuit package is singulated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.