Method for fabricating semiconductor device
US7371628B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2005 |
| Grant date | May 13, 2008 |
| Priority date | — |
| Expiry date | Mar 4, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0172
Abstract
A method for fabricating a semiconductor device is provided. The method mainly involves steps of forming at least one first patterned high stress layer below a silicon substrate, then forming a semiconductor device onto the substrate, and forming at least one second patterned high stress layer on the semiconductor device. According to the method, the characteristics of the PMOS and the NMOS transistors formed on the same wafer may be improved simultaneously, by utilizing the stress of the patterned layers of high stress material. Further, the mobility of the carriers is enhanced, so that the output characteristic of the transistors can be improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.