Patterned backside stress engineering for transistor performance optimization
US7371630B2 · kind B2 · utility
1Cited by
2References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2004 |
| Grant date | May 13, 2008 |
| Priority date | — |
| Expiry date | Apr 8, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Some embodiments of the present invention include selectively inducing back side stress opposite transistor regions to optimize transistor performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.