Oxide-nitride stack gate dielectric
US7371637B2 · kind B2 · utility
5Cited by
12References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2004 |
| Grant date | May 13, 2008 |
| Priority date | — |
| Expiry date | Apr 9, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02233
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making a semiconductor structure comprises forming an oxide layer on a substrate; forming a silicon nitride layer on the oxide layer; annealing the layers in NO; and annealing the layers in ammonia. The equivalent oxide thickness of the oxide layer and the silicon nitride layer together is at most 25 Angstroms.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.