Hybrid interconnect/logic circuits enabling efficient replication of a function in several sub-cycles to save logic and routing resources
US7372297B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2005 |
| Grant date | May 13, 2008 |
| Priority date | — |
| Expiry date | Jun 9, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17758
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Some embodiments provide a reconfigurable IC that implements a design that is designed at a particular design clock rate. The reconfigurable IC includes reconfigurable circuits for performing operations on a set of inputs in the particular design. The IC further includes routing circuits for routing signals to and from the logic circuits to allow the logic circuits to perform the operations. The reconfigurable IC implements the design by having reconfigurable circuits that reconfigure at a rate faster than the design clock rate. For at least one operation which is defined at the design clock rate, the reconfigurable IC replicates the operation set in at least two reconfiguration cycles to reduce consumption of routing circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.