Scannable dynamic logic latch circuit

US7372305B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Hung C. Ngo · Austin, US
• Jente B. Kuang · Austin, US
• James D. Warnock · Somers, US
• Dieter Wendel · Schenefeld, DE

Key dates

• Filing date: Oct 31, 2006
• Grant date: May 13, 2008
• Expiry date: Oct 31, 2026

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318541
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A scannable latch incorporates a logic front end that has at least one dynamic logic gate that has a logic tree that perform the normal Boolean logic operation. The dynamic logic gate is combined a scan pull-down logic tree that is coupled to a scan hold latch output and to the dynamic node of the dynamic logic gate. A scan clock and a normal clock determine whether the logic circuitry is in the normal logic mode or in the scan test mode. A static output latch has at least one input that is responsive logic state of a dynamic node. The evaluated state of the dynamic node is set by either the logic tree of the dynamic logic gate or the scan pull-down logic tree of the scan circuitry in response to the logic state of the scan clock or the normal clock.