System pulse latch and shadow pulse latch coupled to output joining circuit
US7373572B2 · kind B2 · utility
16Cited by
6References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 12, 2005 |
| Grant date | May 13, 2008 |
| Priority date | — |
| Expiry date | Jun 24, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0375
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment, an apparatus includes a system pulse latch to generate at least one system latch signal in response to a data input signal and a pulsed system clock signal; a shadow pulse latch to generate at least one shadow latch signal in response to the data input signal and the pulsed system clock signal; and an output joining circuit, coupled to the system pulse latch and the shadow pulse latch, to provide a data output signal in response to the at least one system latch signal and the at least one shadow latch signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.