Micro-package, multi-stack micro-package, and manufacturing method therefor
US7374972B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2007 |
| Grant date | May 20, 2008 |
| Priority date | — |
| Expiry date | Jul 24, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A micro package, a multi-stack micro package, and a manufacture method therefor are provided. A micro package according to the present invention includes a device substrate for mounting a devices, being a circuit module; a protection cap for protecting the device; bonding substances which, formed by patterning on predetermined areas on the device substrate, bond the device substrate and the protection cap; layers formed on a portion of the device substrate and a portion of the protection cap and exterior sides of the bonding substances; vias which are formed by etching away another portion of the protection cap, and electrically connected to an upper surface of the device substrate through the bonding substances; under barrier metals (UBMs) formed on the vias; and solder bumpers, being connection terminals for an external signal, formed on the UBMs. As stated above, the present invention has advantages of guaranteeing the hermetical sealing since the above layers prevent moisture absorption from outside at the same time of lowering possibility of damages to the device inside the package since the processing temperature drops below 150° upon wafer bonding due to the use of the polym…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.