Method of fabricating field effect transistor (FET) having wire channels
US7374986B2 · kind B2 · utility
85Cited by
6References
20Claims
0Family size
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Key dates
| Filing date | Sep 21, 2007 |
| Grant date | May 20, 2008 |
| Priority date | — |
| Expiry date | Sep 21, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6735
Abstract
In a field effect transistor (FET), and a method of fabricating the same, the FET includes a semiconductor substrate, source and drain regions formed on the semiconductor substrate, a plurality of wire channels electrically connecting the source and drain regions, the plurality of wire channels being arranged in two columns and at least two rows, and a gate dielectric layer surrounding each of the plurality of wire channels and a gate electrode surrounding the gate dielectric layer and each of the plurality of wire channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.