Selective incorporation of charge for transistor channels
US7374998B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2006 |
| Grant date | May 20, 2008 |
| Priority date | — |
| Expiry date | Oct 14, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/668
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device and method for selective placement of charge into a gate stack includes forming gate stacks including a gate dielectric adjacent to a transistor channel and a gate conductor and forming doped regions for transistor operation. A layer rich in a passivating element is deposited over the doped regions and the gate stack, and the layer rich the passivating element is removed from selected transistors. The layer rich in the passivating element is than annealed to drive-in the passivating element to increase a concentration of charge at or near transistor channels on transistors where the layer rich in the passivating element is present. The layer rich in the passivating element is removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.