Semiconductor memory device
US7375399B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2005 |
| Grant date | May 20, 2008 |
| Priority date | — |
| Expiry date | Apr 16, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/104
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is a semiconductor memory device having a logic block and a memory block on the same chip. In the memory device, unit memory cells each include at least two transistors, one of which is a write transistor for storing an electric charge into and releasing it from an electric charge storage node, and the other is a read transistor whose conductance in a channel region provided between a source and drain of the read transistor is modulated dependently on the amount of electric charge stored into or released from the electric charge storage node by the write transistor. The read transistor has a gate-insulating film thicker than that of a transistor provided in the logic block, and uses the same diffusion layer structure as that of the logic block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.