Reconfiguration of programmable logic devices
US7375549B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 2006 |
| Grant date | May 20, 2008 |
| Priority date | — |
| Expiry date | Jul 17, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17764
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Improved reconfiguration techniques are provided for programmable logic devices (PLDs). For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of logic blocks, a plurality of input/output blocks and corresponding input/output pins, and a plurality of configuration memory cells. The configuration memory cells are adapted to store configuration data for configuration of the logic blocks and the input/output blocks. A data port is adapted to provide a clock signal to and receive configuration data from an external memory. A plurality of circuits are adapted to hold the input/output pins in a known logic state during the configuration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.