Fast access memory architecture
US7376038B2 · kind B2 · utility
5Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2006 |
| Grant date | May 20, 2008 |
| Priority date | — |
| Expiry date | Nov 16, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system including a control logic and a storage coupled to the control logic. The storage includes a plurality of bitcells and bitlines used to transfer data between the control logic and the bitcells. The control logic provides an address of a target bitcell to the storage. Within a single clock cycle, the storage uses the address to activate the target bitcell, to precharge bitlines coupled to the target bitcell, and to access the target bitcell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.