Information processing unit, and exception processing method for specific application-purpose operation instruction
US7376820B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2000 |
| Grant date | May 20, 2008 |
| Priority date | — |
| Expiry date | Jun 23, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3879
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In the control section, an operation instruction not prescribing a functional specification, and a unit for processing the specific application-purpose operation instruction is provided within the processor core. The structure of this unit can be changed based on a flexible pipeline structure, and is separately designed for each application field. A register that prescribes a latency from when an instruction of the above unit is issued till when a result can be utilized is also provided in the processor core so as to prevent contention of an output port. Another register that prescribes a latency relating to a constraint of an interval of issuing an instruction of the above unit is also provided in the processor core so as to prevent contention of a resource with the preceding instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.