Ball grid array structures having tape-based circuitry
US7378736B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 13, 2004 |
| Grant date | May 27, 2008 |
| Priority date | — |
| Expiry date | Aug 13, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor device packages formed in accordance with methods of packaging semiconductor dice in grid array-type semiconductor device packages using conventional lead frame or lead lock tape assembly equipment are disclosed. Circuitry-bearing segments having an electrically insulating layer that carries redistribution circuitry and redistributed bond pads and which is supported from beneath by a support layer are secured to the active surface of a semiconductor die. The support layer may comprise an electrically conductive material, which may act as a heat sink or as a ground plane for the packaged semiconductor device. The methods provide increased accuracy with which segments are placed on a semiconductor die relative to the placement accuracies provided when pick-and-place equipment is used to position conventional grid array substrates relative to semiconductor dice.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.