Compliant interconnects for semiconductors and micromachines
US7378742B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2004 |
| Grant date | May 27, 2008 |
| Priority date | — |
| Expiry date | Feb 26, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A compliant interconnect is described that is useful for coupling semiconductor dies to other components. In one embodiment, the interconnect includes a base to couple to a first component and an arch extending from and integral with the base to couple to a second component. The interconnect may be formed by coating a substrate with photoresist, exposing the photoresist with a defined pattern, developing the photoresist, baking the photoresist at a first temperature for a first amount of time to reflow the photoresist, and baking the photoresist at a second higher temperature for a second amount of time to reflow the photoresist.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.