Wafer test head architecture and method of use
US7378860B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2006 |
| Grant date | May 27, 2008 |
| Priority date | — |
| Expiry date | Sep 22, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2886
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A wafer test head and ATE for testing semiconductor wafers. The wafer test head having a plurality of sides that can each be used to test a different semiconductor wafer. The architecture of the wafer test head enables electrical connections to probe card located on two different sides of the wafer test head. Multiple silicon wafers can be tested for proper functionality at the same time or in an interleaved fashion via a single multi-sided wafer test head. The internal architecture of an exemplary wafer test head allows printed circuit cards to be able to electrically connected to multiple wafer test locations on a single wafer test head.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.