Bias for electrostatic discharge protection

US7379281B2 · kind B2 · utility

Assignee

• LSI Logic Corporation · US

Inventors

• William Loh · Petaluma, US
• Minxuan Liu · San Jose, US
• Jau-Wen Chen · Cupertino, US

Key dates

• Filing date: Nov 28, 2005
• Grant date: May 27, 2008
• Expiry date: Jun 8, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/811

Abstract

An electrostatic discharge protection circuit adapted to reduce an electrostatic discharge event on a line of an integrated circuit. The protection circuit includes an NMOS transistor having a source contact that is electrically connected to the line. A drain contact is electrically connected to a logical low voltage, and a gate contact is also electrically connected to the logical low voltage, through a resistor. A substrate bias pump is electrically connected to a back gate of the NMOS transistor, where the bias pump provides a steady state direct current negative bias during normal operation of the integrated circuit when there is no electrostatic discharge event.