Memory controller capable of locating an open command cycle to issue a precharge packet
US7380083B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2005 |
| Grant date | May 27, 2008 |
| Priority date | — |
| Expiry date | May 12, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1626
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller capable of locating an open command cycle for the purpose of issuing a precharge packet to extreme data rate (XDR) dynamic random access memory (DRAM) devices is disclosed. In response to a receipt of two request packets concurrently, a determination is made as to whether one of the request packets includes a non-precharge command and the other one of the request packets includes a precharge command. If one of the request packets includes a non-precharge command and the other one of the request packets includes a precharge command, the request packet having a non-precharge command proceeds. In addition, the precharge command is deferred and its dynamic offset is adjusted accordingly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.