Structure for a multiple-gate FET device and a method for its fabrication
US7381649B2 · kind B2 · utility
20Cited by
2References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2005 |
| Grant date | Jun 3, 2008 |
| Priority date | — |
| Expiry date | Sep 15, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
Abstract
A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.