Fully depleted SOI multiple threshold voltage application
US7382023B2 · kind B2 · utility
9Cited by
7References
31Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2005 |
| Grant date | Jun 3, 2008 |
| Priority date | — |
| Expiry date | Apr 28, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a second region, and a step between the first and second regions. A semiconductor layer overlies the buried dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.