Methods to self-synchronize clocks on multiple chips in a system
US7382844B2 · kind B2 · utility
18Cited by
3References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2005 |
| Grant date | Jun 3, 2008 |
| Priority date | — |
| Expiry date | Aug 5, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of self-synchronizing clocks in a multiple chip system, by assigning one chip as the master chip and the other chips as slave chips. A training signal is sent from master chip to the slave chips to determine the latency from the master chip to a slave chip, and then a synchronization signal is sent out to synchronize the “time zero” of the chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.