Verification of scheduling in the presence of loops using uninterpreted symbolic simulation
US7383166B2 · kind B2 · utility
57Cited by
14References
10Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 14, 2004 |
| Grant date | Jun 3, 2008 |
| Priority date | — |
| Expiry date | May 3, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of checking correctness of scheduling of a circuit where a schedule for the circuit is obtained from a behavioral description. The method comprising extracting loop invariants to determine a sufficient set of acyclic threads when loops are present, performing symbolic simulation to extract the above loop invariants, and proving equivalence of the acyclic threads. Systems, computer systems and computer program products that incorporate the techniques of verification and correctness checking according to the present invention have also been disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.