Method and apparatus for prefetching data to a lower level cache memory
US7383418B2 · kind B2 · utility
8Cited by
20References
2Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 1, 2004 |
| Grant date | Jun 3, 2008 |
| Priority date | — |
| Expiry date | Dec 25, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A prefetching scheme to detect when a load misses the lower level cache and hits the next level cache. Consequently, the prefetching scheme utilizes the previous information for the cache miss to the lower level cache and hit to the next higher level of cache memory that may result in initiating a sidedoor prefetch load for fetching the previous or next cache line into the lower level cache. In order to generate an address for the sidedoor prefetch, a history of cache access is maintained in a queue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.