Non-inline transaction error correction
US7383464B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2003 |
| Grant date | Jun 3, 2008 |
| Priority date | — |
| Expiry date | Apr 10, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1407
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Non-inline transaction error correction is disclosed. Where a transaction being processed in a pipeline is determined to include a correctable error, it is output, or drained, from the pipeline into an error queue. The pipeline is switched from a normal mode of operation to a correction mode of operation. In the correction mode, a correction command is inserted into and processed within the pipeline to correct the error within the transaction. The pipeline is switched from the correction mode of operation to a restart mode of operation. In the restart mode, the transaction is reprocessed within the pipeline. The pipeline is then switched from the restart mode of operation back to the normal mode of operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.