Scanning latches using selecting array
US7383480B2 · kind B2 · utility
3Cited by
12References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2004 |
| Grant date | Jun 3, 2008 |
| Priority date | — |
| Expiry date | Apr 11, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for scanning data from a specific latch in a matrix array of latches. The matrix array is made up of vertical selector lines and horizontal data lines. Each latch is coupled at an intersection of a selector line and a data line by a transistor. By turning on the transistor, the contents of the latch can be selectively read or written to.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.